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#### 3.17.27 IBM RS/6000 and PowerPC Options

These -m options are defined for the IBM RS/6000 and PowerPC:

`-mpower`
`-mno-power`
`-mpower2`
`-mno-power2`
`-mpowerpc`
`-mno-powerpc`
`-mpowerpc-gpopt`
`-mno-powerpc-gpopt`
`-mpowerpc-gfxopt`
`-mno-powerpc-gfxopt`
`-mpowerpc64`
`-mno-powerpc64`
`-mmfcrf`
`-mno-mfcrf`
`-mpopcntb`
`-mno-popcntb`
`-mfprnd`
`-mno-fprnd`
`-mcmpb`
`-mno-cmpb`
`-mmfpgpr`
`-mno-mfpgpr`
`-mhard-dfp`
`-mno-hard-dfp`
  GCC supports two related instruction set architectures for the RS/6000 and PowerPC. The POWER instruction set are those instructions supported by the rios chip set used in the original RS/6000 systems and the PowerPC instruction set is the architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and the IBM 4xx, 6xx, and follow-on microprocessors.

  Neither architecture is a subset of the other. However there is a large common subset of instructions supported by both. An MQ register is included in processors supporting the POWER architecture.

  You use these options to specify which instructions are available on the processor you are using. The default value of these options is determined when configuring GCC. Specifying the -mcpu=cpu_type overrides the specification of these options. We recommend you use the -mcpu=cpu_type option rather than the options listed above.

  The -mpower option allows GCC to generate instructions that are found only in the POWER architecture and to use the MQ register. Specifying -mpower2 implies -power and also allows GCC to generate instructions that are present in the POWER2 architecture but not the original POWER architecture.

  The -mpowerpc option allows GCC to generate instructions that are found only in the 32-bit subset of the PowerPC architecture. Specifying -mpowerpc-gpopt implies -mpowerpc and also allows GCC to use the optional PowerPC architecture instructions in the General Purpose group, including floating-point square root. Specifying -mpowerpc-gfxopt implies -mpowerpc and also allows GCC to use the optional PowerPC architecture instructions in the Graphics group, including floating-point select.

  The -mmfcrf option allows GCC to generate the move from condition register field instruction implemented on the POWER4 processor and other processors that support the PowerPC V2.01 architecture. The -mpopcntb option allows GCC to generate the popcount and double precision FP reciprocal estimate instruction implemented on the POWER5 processor and other processors that support the PowerPC V2.02 architecture. The -mfprnd option allows GCC to generate the FP round to integer instructions implemented on the POWER5+ processor and other processors that support the PowerPC V2.03 architecture. The -mcmpb option allows GCC to generate the compare bytes instruction implemented on the POWER6 processor and other processors that support the PowerPC V2.05 architecture. The -mmfpgpr option allows GCC to generate the FP move to/from general purpose register instructions implemented on the POWER6X processor and other processors that support the extended PowerPC V2.05 architecture. The -mhard-dfp option allows GCC to generate the decimal floating point instructions implemented on some POWER processors.

  The -mpowerpc64 option allows GCC to generate the additional 64-bit instructions that are found in the full PowerPC64 architecture and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to -mno-powerpc64.

  If you specify both -mno-power and -mno-powerpc, GCC will use only the instructions in the common subset of both architectures plus some special AIX common-mode calls, and will not use the MQ register. Specifying both -mpower and -mpowerpc permits GCC to use any instruction from either architecture and to allow use of the MQ register; specify this for the Motorola MPC601.

`-mnew-mnemonics`
`-mold-mnemonics`
  Select which mnemonics to use in the generated assembler code. With -mnew-mnemonics, GCC uses the assembler mnemonics defined for the PowerPC architecture. With -mold-mnemonics it uses the assembler mnemonics defined for the POWER architecture. Instructions defined in only one architecture have only one mnemonic; GCC uses that mnemonic irrespective of which of these options is specified.

  GCC defaults to the mnemonics appropriate for the architecture in use. Specifying -mcpu=cpu_type sometimes overrides the value of these option. Unless you are building a cross-compiler, you should normally not specify either -mnew-mnemonics or -mold-mnemonics, but should instead accept the default.

`-mcpu=`cpu_type
  Set architecture type, register usage, choice of mnemonics, and instruction scheduling parameters for machine type cpu_type. Supported values for cpu_type are 401, 403, 405, 405fp, 440, 440fp, 505, 601, 602, 603, 603e, 604, 604e, 620, 630, 740, 7400, 7450, 750, 801, 821, 823, 860, 970, 8540, ec603e, G3, G4, G5, power, power2, power3, power4, power5, power5+, power6, power6x, common, powerpc, powerpc64, rios, rios1, rios2, rsc, and rs64.

  -mcpu=common selects a completely generic processor. Code generated under this option will run on any POWER or PowerPC processor. GCC will use only the instructions in the common subset of both architectures, and will not use the MQ register. GCC assumes a generic processor model for scheduling purposes.

  -mcpu=power, -mcpu=power2, -mcpu=powerpc, and -mcpu=powerpc64 specify generic POWER, POWER2, pure 32-bit PowerPC (i.e., not MPC601), and 64-bit PowerPC architecture machine types, with an appropriate, generic processor model assumed for scheduling purposes.

  The other options specify a specific processor. Code generated under those options will run best on that processor, and may not run at all on others.

  The -mcpu options automatically enable or disable the following options:

                -maltivec  -mfprnd  -mhard-float  -mmfcrf  -mmultiple
                -mnew-mnemonics  -mpopcntb  -mpower  -mpower2  -mpowerpc64
                -mpowerpc-gpopt  -mpowerpc-gfxopt  -mstring  -mmulhw  -mdlmzb  -mmfpgpr

  The particular options set for any particular CPU will vary between compiler versions, depending on what setting seems to produce optimal code for that CPU; it doesn't necessarily reflect the actual hardware's capabilities. If you wish to set an individual option to a particular value, you may specify it after the -mcpu option, like -mcpu=970 -mno-altivec.

  On AIX, the -maltivec and -mpowerpc64 options are not enabled or disabled by the -mcpu option at present because AIX does not have full support for these options. You may still enable or disable them individually if you're sure it'll work in your environment.

`-mtune=`cpu_type
  Set the instruction scheduling parameters for machine type cpu_type, but do not set the architecture type, register usage, or choice of mnemonics, as -mcpu=cpu_type would. The same values for cpu_type are used for -mtune as for -mcpu. If both are specified, the code generated will use the architecture, registers, and mnemonics set by -mcpu, but the scheduling parameters set by -mtune.
`-mswdiv`
`-mno-swdiv`
  Generate code to compute division as reciprocal estimate and iterative refinement, creating opportunities for increased throughput. This feature requires: optional PowerPC Graphics instruction set for single precision and FRE instruction for double precision, assuming divides cannot generate user-visible traps, and the domain values not include Infinities, denormals or zero denominator.
`-maltivec`
`-mno-altivec`
  Generate code that uses (does not use) AltiVec instructions, and also enable the use of built-in functions that allow more direct access to the AltiVec instruction set. You may also need to set -mabi=altivec to adjust the current ABI with AltiVec ABI enhancements.
`-mvrsave`
`-mno-vrsave`
  Generate VRSAVE instructions when generating AltiVec code.
`-msecure-plt`
  Generate code that allows ld and ld.so to build executables and shared libraries with non-exec .plt and .got sections. This is a PowerPC 32-bit SYSV ABI option.
`-mbss-plt`
  Generate code that uses a BSS .plt section that ld.so fills in, and requires .plt and .got sections that are both writable and executable. This is a PowerPC 32-bit SYSV ABI option.
`-misel`
`-mno-isel`
  This switch enables or disables the generation of ISEL instructions.
`-misel=`yes/no
  This switch has been deprecated. Use -misel and -mno-isel instead.
`-mspe`
`-mno-spe`
  This switch enables or disables the generation of SPE simd instructions.
`-mpaired`
`-mno-paired`
  This switch enables or disables the generation of PAIRED simd instructions.
`-mspe=`yes/no
  This option has been deprecated. Use -mspe and -mno-spe instead.
`-mfloat-gprs=`yes/single/double/no
`-mfloat-gprs`
  This switch enables or disables the generation of floating point operations on the general purpose registers for architectures that support it.

  The argument yes or single enables the use of single-precision floating point operations.

  The argument double enables the use of single and double-precision floating point operations.

  The argument no disables floating point operations on the general purpose registers.

  This option is currently only available on the MPC854x.

`-m32`
`-m64`
  Generate code for 32-bit or 64-bit environments of Darwin and SVR4 targets (including GNU/Linux). The 32-bit environment sets int, long and pointer to 32 bits and generates code that runs on any PowerPC variant. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits, and generates code for PowerPC64, as for -mpowerpc64.
`-mfull-toc`
`-mno-fp-in-toc`
`-mno-sum-in-toc`
`-mminimal-toc`
  Modify generation of the TOC (Table Of Contents), which is created for every executable file. The -mfull-toc option is selected by default. In that case, GCC will allocate at least one TOC entry for each unique non-automatic variable reference in your program. GCC will also place floating-point constants in the TOC. However, only 16,384 entries are available in the TOC.

  If you receive a linker error message that saying you have overflowed the available TOC space, you can reduce the amount of TOC space used with the -mno-fp-in-toc and -mno-sum-in-toc options. -mno-fp-in-toc prevents GCC from putting floating-point constants in the TOC and -mno-sum-in-toc forces GCC to generate code to calculate the sum of an address and a constant at run-time instead of putting that sum into the TOC. You may specify one or both of these options. Each causes GCC to produce very slightly slower and larger code at the expense of conserving TOC space.

  If you still run out of space in the TOC even when you specify both of these options, specify -mminimal-toc instead. This option causes GCC to make only one TOC entry for every file. When you specify this option, GCC will produce code that is slower and larger but which uses extremely little TOC space. You may wish to use this option only on files that contain less frequently executed code.

`-maix64`
`-maix32`
  Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit `long` type, and the infrastructure needed to support them. Specifying -maix64 implies -mpowerpc64 and -mpowerpc, while -maix32 disables the 64-bit ABI and implies -mno-powerpc64. GCC defaults to -maix32.
`-mxl-compat`
`-mno-xl-compat`
  Produce code that conforms more closely to IBM XL compiler semantics when using AIX-compatible ABI. Pass floating-point arguments to prototyped functions beyond the register save area (RSA) on the stack in addition to argument FPRs. Do not assume that most significant double in 128-bit long double value is properly rounded when comparing values and converting to double. Use XL symbol names for long double support routines.

  The AIX calling convention was extended but not initially documented to handle an obscure K&R C case of calling a function that takes the address of its arguments with fewer arguments than declared. IBM XL compilers access floating point arguments which do not fit in the RSA from the stack when a subroutine is compiled without optimization. Because always storing floating-point arguments on the stack is inefficient and rarely needed, this option is not enabled by default and only is necessary when calling subroutines compiled by IBM XL compilers without optimization.

`-mpe`
  Support IBM RS/6000 SP Parallel Environment (PE). Link an application written to use message passing with special startup code to enable the application to run. The system must have PE installed in the standard location (/usr/lpp/ppe.poe/), or the specs file must be overridden with the -specs= option to specify the appropriate directory location. The Parallel Environment does not support threads, so the -mpe option and the -pthread option are incompatible.
`-malign-natural`
`-malign-power`
  On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option -malign-natural overrides the ABI-defined alignment of larger types, such as floating-point doubles, on their natural size-based boundary. The option -malign-power instructs GCC to follow the ABI-specified alignment rules. GCC defaults to the standard alignment defined in the ABI.

  On 64-bit Darwin, natural alignment is the default, and -malign-power is not supported.

`-msoft-float`
`-mhard-float`
  Generate code that does not use (uses) the floating-point register set. Software floating point emulation is provided if you use the -msoft-float option, and pass the option to GCC when linking.
`-mmultiple`
`-mno-multiple`
  Generate code that uses (does not use) the load multiple word instructions and the store multiple word instructions. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use -mmultiple on little endian PowerPC systems, since those instructions do not work when the processor is in little endian mode. The exceptions are PPC740 and PPC750 which permit the instructions usage in little endian mode.
`-mstring`
`-mno-string`
  Generate code that uses (does not use) the load string instructions and the store string word instructions to save multiple registers and do small block moves. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use -mstring on little endian PowerPC systems, since those instructions do not work when the processor is in little endian mode. The exceptions are PPC740 and PPC750 which permit the instructions usage in little endian mode.
`-mupdate`
`-mno-update`
  Generate code that uses (does not use) the load or store instructions that update the base register to the address of the calculated memory location. These instructions are generated by default. If you use -mno-update, there is a small window between the time that the stack pointer is updated and the address of the previous frame is stored, which means code that walks the stack frame across interrupts or signals may get corrupted data.
`-mfused-madd`
`-mno-fused-madd`
  Generate code that uses (does not use) the floating point multiply and accumulate instructions. These instructions are generated by default if hardware floating is used.
`-mmulhw`
`-mno-mulhw`
  Generate code that uses (does not use) the half-word multiply and multiply-accumulate instructions on the IBM 405 and 440 processors. These instructions are generated by default when targetting those processors.
`-mdlmzb`
`-mno-dlmzb`
  Generate code that uses (does not use) the string-search dlmzb instruction on the IBM 405 and 440 processors. This instruction is generated by default when targetting those processors.
`-mno-bit-align`
`-mbit-align`
  On System V.4 and embedded PowerPC systems do not (do) force structures and unions that contain bit-fields to be aligned to the base type of the bit-field.

  For example, by default a structure containing nothing but 8 `unsigned` bit-fields of length 1 would be aligned to a 4 byte boundary and have a size of 4 bytes. By using -mno-bit-align, the structure would be aligned to a 1 byte boundary and be one byte in size.

`-mno-strict-align`
`-mstrict-align`
  On System V.4 and embedded PowerPC systems do not (do) assume that unaligned memory references will be handled by the system.
`-mrelocatable`
`-mno-relocatable`
  On embedded PowerPC systems generate code that allows (does not allow) the program to be relocated to a different address at runtime. If you use -mrelocatable on any module, all objects linked together must be compiled with -mrelocatable or -mrelocatable-lib.
`-mrelocatable-lib`
`-mno-relocatable-lib`
  On embedded PowerPC systems generate code that allows (does not allow) the program to be relocated to a different address at runtime. Modules compiled with -mrelocatable-lib can be linked with either modules compiled without -mrelocatable and -mrelocatable-lib or with modules compiled with the -mrelocatable options.
`-mno-toc`
`-mtoc`
  On System V.4 and embedded PowerPC systems do not (do) assume that register 2 contains a pointer to a global area pointing to the addresses used in the program.
`-mlittle`
`-mlittle-endian`
  On System V.4 and embedded PowerPC systems compile code for the processor in little endian mode. The -mlittle-endian option is the same as -mlittle.
`-mbig`
`-mbig-endian`
  On System V.4 and embedded PowerPC systems compile code for the processor in big endian mode. The -mbig-endian option is the same as -mbig.
`-mdynamic-no-pic`
  On Darwin and Mac OS X systems, compile code so that it is not relocatable, but that its external references are relocatable. The resulting code is suitable for applications, but not shared libraries.
`-mprioritize-restricted-insns=`priority
  This option controls the priority that is assigned to dispatch-slot restricted instructions during the second scheduling pass. The argument priority takes the value 0/1/2 to assign no/highest/second-highest priority to dispatch slot restricted instructions.
`-msched-costly-dep=`dependence_type
  This option controls which dependences are considered costly by the target during instruction scheduling. The argument dependence_type takes one of the following values: no: no dependence is costly, all: all dependences are costly, true_store_to_load: a true dependence from store to load is costly, store_to_load: any dependence from store to load is costly, number: any dependence which latency >= number is costly.
`-minsert-sched-nops=`scheme
  This option controls which nop insertion scheme will be used during the second scheduling pass. The argument scheme takes one of the following values: no: Don't insert nops. pad: Pad with nops any dispatch group which has vacant issue slots, according to the scheduler's grouping. regroup_exact: Insert nops to force costly dependent insns into separate groups. Insert exactly as many nops as needed to force an insn to a new group, according to the estimated processor grouping. number: Insert nops to force costly dependent insns into separate groups. Insert number nops to force an insn to a new group.
`-mcall-sysv`
  On System V.4 and embedded PowerPC systems compile code using calling conventions that adheres to the March 1995 draft of the System V Application Binary Interface, PowerPC processor supplement. This is the default unless you configured GCC using powerpc-*-eabiaix.
`-mcall-sysv-eabi`
  Specify both -mcall-sysv and -meabi options.
`-mcall-sysv-noeabi`
  Specify both -mcall-sysv and -mno-eabi options.
`-mcall-solaris`
  On System V.4 and embedded PowerPC systems compile code for the Solaris operating system.
`-mcall-linux`
  On System V.4 and embedded PowerPC systems compile code for the Linux-based GNU system.
`-mcall-gnu`
  On System V.4 and embedded PowerPC systems compile code for the Hurd-based GNU system.
`-mcall-netbsd`
  On System V.4 and embedded PowerPC systems compile code for the NetBSD operating system.
`-maix-struct-return`
  Return all structures in memory (as specified by the AIX ABI).
`-msvr4-struct-return`
  Return structures smaller than 8 bytes in registers (as specified by the SVR4 ABI).
`-mabi=`abi-type
  Extend the current ABI with a particular extension, or remove such extension. Valid values are altivec, no-altivec, spe, no-spe, ibmlongdouble, ieeelongdouble.
`-mabi=spe`
  Extend the current ABI with SPE ABI extensions. This does not change the default ABI, instead it adds the SPE ABI extensions to the current ABI.
`-mabi=no-spe`
  Disable Booke SPE ABI extensions for the current ABI.
`-mabi=ibmlongdouble`
  Change the current ABI to use IBM extended precision long double. This is a PowerPC 32-bit SYSV ABI option.
`-mabi=ieeelongdouble`
  Change the current ABI to use IEEE extended precision long double. This is a PowerPC 32-bit Linux ABI option.
`-mprototype`
`-mno-prototype`
  On System V.4 and embedded PowerPC systems assume that all calls to variable argument functions are properly prototyped. Otherwise, the compiler must insert an instruction before every non prototyped call to set or clear bit 6 of the condition code register (CR) to indicate whether floating point values were passed in the floating point registers in case the function takes a variable arguments. With -mprototype, only calls to prototyped variable argument functions will set or clear the bit.
`-msim`
  On embedded PowerPC systems, assume that the startup module is called sim-crt0.o and that the standard C libraries are libsim.a and libc.a. This is the default for powerpc-*-eabisim configurations.
`-mmvme`
  On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libmvme.a and libc.a.
`-mads`
  On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libads.a and libc.a.
`-myellowknife`
  On embedded PowerPC systems, assume that the startup module is called crt0.o and the standard C libraries are libyk.a and libc.a.
`-mvxworks`
  On System V.4 and embedded PowerPC systems, specify that you are compiling for a VxWorks system.
`-mwindiss`
  Specify that you are compiling for the WindISS simulation environment.
`-memb`
  On embedded PowerPC systems, set the PPC_EMB bit in the ELF flags header to indicate that eabi extended relocations are used.
`-meabi`
`-mno-eabi`
  On System V.4 and embedded PowerPC systems do (do not) adhere to the Embedded Applications Binary Interface (eabi) which is a set of modifications to the System V.4 specifications. Selecting -meabi means that the stack is aligned to an 8 byte boundary, a function `__eabi` is called to from `main` to set up the eabi environment, and the -msdata option can use both `r2` and `r13` to point to two separate small data areas. Selecting -mno-eabi means that the stack is aligned to a 16 byte boundary, do not call an initialization function from `main`, and the -msdata option will only use `r13` to point to a single small data area. The -meabi option is on by default if you configured GCC using one of the powerpc*-*-eabi* options.
`-msdata=eabi`
  On System V.4 and embedded PowerPC systems, put small initialized `const` global and static data in the .sdata2 section, which is pointed to by register `r2`. Put small initialized non-`const` global and static data in the .sdata section, which is pointed to by register `r13`. Put small uninitialized global and static data in the .sbss section, which is adjacent to the .sdata section. The -msdata=eabi option is incompatible with the -mrelocatable option. The -msdata=eabi option also sets the -memb option.
`-msdata=sysv`
  On System V.4 and embedded PowerPC systems, put small global and static data in the .sdata section, which is pointed to by register `r13`. Put small uninitialized global and static data in the .sbss section, which is adjacent to the .sdata section. The -msdata=sysv option is incompatible with the -mrelocatable option.
`-msdata=default`
`-msdata`
  On System V.4 and embedded PowerPC systems, if -meabi is used, compile code the same as -msdata=eabi, otherwise compile code the same as -msdata=sysv.
`-msdata-data`
  On System V.4 and embedded PowerPC systems, put small global data in the .sdata section. Put small uninitialized global data in the .sbss section. Do not use register `r13` to address small data however. This is the default behavior unless other -msdata options are used.
`-msdata=none`
`-mno-sdata`
  On embedded PowerPC systems, put all initialized global and static data in the .data section, and all uninitialized data in the .bss section.
`-G` num
  On embedded PowerPC systems, put global and static items less than or equal to num bytes into the small data or bss sections instead of the normal data or bss section. By default, num is 8. The -G num switch is also passed to the linker. All modules should be compiled with the same -G num value.
`-mregnames`
`-mno-regnames`
  On System V.4 and embedded PowerPC systems do (do not) emit register names in the assembly language output using symbolic forms.
`-mlongcall`
`-mno-longcall`
  By default assume that all calls are far away so that a longer more expensive calling sequence is required. This is required for calls further than 32 megabytes (33,554,432 bytes) from the current location. A short call will be generated if the compiler knows the call cannot be that far away. This setting can be overridden by the `shortcall` function attribute, or by `#pragma longcall(0)`.

  Some linkers are capable of detecting out-of-range calls and generating glue code on the fly. On these systems, long calls are unnecessary and generate slower code. As of this writing, the AIX linker can do this, as can the GNU linker for PowerPC/64. It is planned to add this feature to the GNU linker for 32-bit PowerPC systems as well.

  On Darwin/PPC systems, `#pragma longcall` will generate “jbsr callee, L42”, plus a “branch island” (glue code). The two target addresses represent the callee and the “branch island”. The Darwin/PPC linker will prefer the first address and generate a “bl callee” if the PPC “bl” instruction will reach the callee directly; otherwise, the linker will generate “bl L42” to call the “branch island”. The “branch island” is appended to the body of the calling function; it computes the full 32-bit address of the callee and jumps to it.

  On Mach-O (Darwin) systems, this option directs the compiler emit to the glue for every direct call, and the Darwin linker decides whether to use or discard it.

  In the future, we may cause GCC to ignore all longcall specifications when the linker is known to generate glue.

`-pthread`
  Adds support for multithreading with the pthreads library. This option sets flags for both the preprocessor and linker.